library ieee;
use ieee.std_logic_1164.all;

entity testbench_divide_16 is
end testbench_divide_16;

architecture test of testbench_divide_16 is

	component divide_16
		port (
			nclk_i       : in  std_logic;
			reset_i		 : in  std_logic;
			nclk_div16_o : out std_logic 
		);
	end component;

	signal nclk       : std_logic;
	signal reset	  : std_logic;
	signal nclk_div16 : std_logic;

begin

	divide_16_inst : divide_16
	port map (
		nclk_i 			=> nclk,
		reset_i			=> reset,
		nclk_div16_o	=> nclk_div16
	);

	gen_clk : process
	begin
		nclk <= '0';
		wait for 10 ns;
		nclk <= '1';
		wait for 10 ns;
	end process;

	gen_test : process
	begin
		wait for 100 ns;

		reset <= '1';

		wait for 10 ns;

		reset <= '0';
	
		wait;
	end process;

end test;
